Kang L. Wang, Ph.D.
Kang L. Wang.
Raytheon Professor of Physical Science and Electronics
Henry Samueli School of Engineering and Applied Science, UCLA
Speech Title: 
"Nonvolatile Memory/Storage for Electronics Systems"
Bio: 

Kang L. Wang has held 18 patents and published over 500 journal papers. He was the inventor of strained layer MOSFET, quantum SRAM cell, and band-aligned superlattices and voltage control magnetism, etc.. His current on-going projects are aimed at semiconductor/spintronics and correlated systems for low power applications.

Professor Wang received many awards, including Semiconductor Industry Association University Research Award; IBM Faculty Award; Guggenheim Fellow; IEEE Fellow; TSMC Honor Lectureship Award; Honoris Causa at Politechnico University, Torino, Italy; European Material Research Society Meeting Best paper award; the Semiconductor Research Corporation Technical Excellence Achievement Award and SRC Outstanding University Service Award. He also served as the Honorary Professors of Tsinghua University, Nanjing University, Xian Jiaotung University, Institute of Semiconductor, Academy of Science, China and Polytecnico University, Torino, Italy.

Professor Wang currently serves as the Editor-In-Chief for the IEEE Transaction of Nanotechnology (TNANO) and is on the editorial board of the Encyclopedia of Nanoscience and Nanotechnology TM (American Scientific publishers). He also serves as the Series Editor of Nanoscience and Technology Series for Artech House, Boston, MA and the editorial board for Journal of Spins, Handbooks of Semiconductor Nanostructures and Nanodevices, as well as several other journals.

Since 2003, Professor Wang has been serving as the Director of Marco Focus Center on Functional Engineered Nano Architectonics (FENA), an interdisciplinary Research Center, funded by Semiconductor Industry Association and Department of Defense to address the challenge of low-dissipation information processing technology beyond scaled CMOS. The FENA Center involves 12 universities across the USA with over 40 participating faculty members. Since 2006, he has also been the Director of the Western Institute of Nanoelectronics (WIN) – a coordinated multi-project Research Institute. WIN is funded by NRI, Intel and the State of California.

Abstract
The landscape of nonvolatile memory/storage technology will be discussed. Energy-efficient MgO-based magnetic memory using tunnel junction (MTJ) bits has emerged for high-speed, low energy, high density applications. I will discuss these magnetic memory technologies, including spin-transfer- magnetoresistive random access memory (STT-MRAM)[1] and magnetoelectric memory (MeRAM). These types of device may be integrated directly on top of front-end processed CMOS using back-end process. They will enables standalone and imbedded applications, making possible new generations of nonvolatile instant-on electronics and other systems.

[1] P.K. Amiri, Z.M. Zeng, P. Upadhyaya, G. Rowlands, H. Zhao, I.N. Krivorotov, J.-P. Wang, H.W. Jiang, J.A. Katine, J. Langer, K. Galatsis, K.L. Wang, "Low Write-Energy Magnetic Tunnel Junctions for High-Speed Spin-Transfer-Torque MRAM", IEEE Electron Device Letters, Vol. 32, No. 1, pp. 57-59, January 2011.

October 16-17, 2012

The Rose Project

Western Digital